The present invention relates to circuitized printed wiring board structures and especially to via barrels having enhanced copper adhesion. The enhanced adhesiveness of the copper plating provides improved performance in high temperature assembly operations. The present invention also provides a method for fabricating via barrels plated with highly adherent copper.
In the manufacture of printed circuit boards, sometimes known as printed wiring boards, it is now commonplace to produce printed circuitry on both sides of a planar rigid or flexible insulating substrate. Of increased importance is the manufacture of multilayer printed circuits. In these products, the board consists of parallel, planar, alternating innerlayers of insulating substrate material and conductive metal. The exposed outer sides of the laminated structure are provided with circuit patterns as with double-sided boards, and the metal innerlayers may themselves contain circuit patterns.
In double-sided and multilayer printed circuit boards, it is necessary to provide conductive interconnection between or among the various layers or sides of the board containing conductive circuitry. This is commonly achieved by providing metallized, conductive thru-holes in the board communicating with the sides and layers requiring electrical interconnection. For some applications, it is desired that electrical connection be made with up to all of the conductive layers. In such case, thru-holes are provided through the entire thickness of the board. For other applications, it is desired to provide electrical connection between the circuitry on one face of the board and one or more of the inner circuit layers. In those cases, blind via, passing only part way through the board are provided. For purposes of this application, the terms xe2x80x9cthru-hole,xe2x80x9d xe2x80x9cblind via,xe2x80x9d and xe2x80x9cviaxe2x80x9d are used interchangeably.
To provide the desired circuit pattern on the board, the art has developed a variety of manufacturing sequences, many of which fall into the broad categories of xe2x80x9csubtractivexe2x80x9d or xe2x80x9cadditivexe2x80x9d techniques. Common to subtractive processes is the need to etch away (or subtract) metal to expose substrate surface in areas where no circuitry is desired. Additive processes, on the other hand, begin with exposed substrate surfaces (or thin commoning metallization layers for additive electroplate) and build up thereon metallization in desired areas, the desired areas being those not masked by a previously-applied pattern of plating resist material (e.g., photoresist in positive pattern).
Typically, via holes are drilled or punched into or through the board structure at desired locations. Drilling or punching provides newly-exposed surfaces including via barrel surfaces and via peripheral entry surfaces. The dielectric substrate, comprising a top surface, a bottom surface, and at least one exposed via hole surface, consisting partly or entirely of insulating material, is then metallized, generally by utilization of electroless metal depositing techniques.
In the manufacture of circuitized printed wiring board carrier structures, a dielectric sheet material is employed as the substrate. The substrate typically is an organic material, such as fiberglass-reinforced epoxy resin (FR4), polytetrafluoroethylene, etc. Since the dielectric substrate is nonconductive, in order to plate on the substrate, the substrate must be seeded or catalyzed prior to the deposition of metal onto the substrate. The electroless plating of copper onto a substrate is well-known in the art. For instance, an electroless or autocatalytic copper plating bath usually contains a cupric salt, a reducing agent for the cupric salt, a chelating or complexing agent, and a pH adjustor. In addition, if the surface being plated is not already catalytic for the deposition of the desired metal, a suitable catalyst is deposited onto the surface prior to contact with the plating bath. Among the more widely employed procedures for catalyzing a surface is the use of stannous chloride sensitizing solution and a palladium chloride activator to form a layer of metallic palladium particles.
Copper is not highly adherent to the materials typically used as the dielectric substrate. The deposited copper is generally anchored to the exposed inner copper layers more than the dielectric. During subsequent process steps, especially thermal cycling, the copper xe2x80x9cbarrelxe2x80x9d has a tendency to crack or delaminate, causing open circuits. Therefore a requirement exists for means to increase the bonding strength of the copper to the substrate.
The present invention provides the desired increased durability of via barrels without the requirement for many of the additional processing steps and materials used in prior art solutions. For example, Takahashi et al. (U.S. Pat. No. 5,309,632) require a double resist process and the application of an adhesive layer to the entire board surface. Their method also plates nickel over the entire board surface and then strip the nickel in excess of the circuitization.
It is known in the prior art to provide a layer of nickel over substantially the entire surface of the wiring board, print copper circuitization over the nickel, and then to strip excess nickel. Examples of this practice include Cane (U.S. Pat. No. 5,648,125). Stripping of Ni after application of Cu results in a line substantially trapezoidal in cross-section, with portions of the Cu wiring cantilevered, unstably over the Ni. In addition to plating Ni only where circuitization is to be invoked, the process of the present invention results in lines of substantially rectangular cross-section and thus a more stable bonding of the Cu.
Another disadvantage of prior art methods is exemplified by Knopp (U.S. Pat. No. 5,758,412) where the thickness of the underplated metal is too thin to provide circuitization robustness against subsequent high temperature assembly steps.
The present invention provides via barrels exhibiting high copper to substrate adhesion. The present invention makes possible via barrels that survive the thermal stresses of high temperature assembly and have a longer thermal cycle life than bare copper barrels.
More specifically, the present invention provides via barrels which comprise: a wiring board of dielectric material wherein a plurality of via are defined; a catalyst seed layer located on the inner surface of the via within the dielectric material; a layer of nickel deposited on top of the catalyst seed layer; and a layer of copper plating in the openings and over the layer of nickel.
It is an aspect of the invention to provide more robust metallization of via barrels by providing multiple metallization layers.
It is an aspect of the invention to provide more robust metallization of via barrels by providing metallization of via barrel surfaces including via peripheral entry surfaces, and providing metallization of via surfaces continuous with metallization of the top and bottom surfaces and the conductive layers of the dielectric substrate.
It is an aspect of the invention to provide more robust metallization of via barrels by providing a circuitized printed wiring board comprising a dielectric substrate having a top surface, and a bottom surface, and at least one via, the at least one via having a via barrel surface and at least one via peripheral entry surface; a first metallization layer deposited on the via barrel surface and the at least one via peripheral entry surface of the at least one via, the top surface, and the bottom surface of the dielectric substrate; a second metallization layer deposited on the first metallization layer on the via barrel surface and the at least one via peripheral entry surface of the at least one via, and selectively deposited on the first metallization layer on the top surface and the bottom surface of said dielectric substrate; and a third metallization layer deposited on the second metallization layer on the first metallization layer on the via barrel surface and the at least one via peripheral entry surface of the at least one via, and selectively deposited on the second metallization layer on the first metallization layer on the top surface and the bottom surface of the dielectric substrate.
The present invention also relates to fabricating the above disclosed printed circuit board. The method comprises: providing a board having a top surface and a bottom surface and comprised of one or more layers of dielectric material and optionally one or more inner conductive layers which are optionally personalized by provision of a pattern such as a circuit pattern; depositing a catalyst seed layer on the layer of dielectric material; depositing a layer of nickel on top of the catalyst seed layer; and depositing a layer of copper plating over the layer of nickel.
Metallization of the dielectric substrate comprises providing a first metallization layer termed a catalytic seed layer and is typically palladium and tin; providing a second metallization layer wherein the layer is chosen from the group VIII and Group IB transition metals and is typically nickel; and providing a third metallization layer, typically copper. Alternatively, the catalytic seed layer is thus termed and the nickel and copper layers are respectively termed the xe2x80x9cfirst metallizationxe2x80x9d and the xe2x80x9csecond metallization.xe2x80x9d
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.